Nơi làm việc:
Hồ Chí Minh
Địa chỉ: Incubation Building, Lot D.01, Tan Thuan Street, Tan Thuan Export Processing Zone, Tan Thuan Dong Ward, Dist 7, HCMC
Mức lương: Thỏa thuận
Chức vụ: Trưởng Nhóm
Kinh nghiệm: Chưa có kinh nghiệm
Hình thức làm việc:
Yêu cầu bằng cấp: Không yêu cầu
Yêu cầu giới tính: Không yêu cầu
Hồ Chí Minh
Mô tả công việc
In this role, you will have the opportunity to work in the package and system interconnect connect engineering group. You will be part of a dedicated team, open communications, empowerment, innovation, teamwork and customer success are the foundations of the team. You will work with Signal Integrity team to verify signal characteristics and optimize signal routing. Thus, you set your own limits for learning and achievements. A motivated Signal Integrity Engineer will contribute to the development of our next generation product.
• Extract S-parameter model for the DDR3/4/5, and the SerDes interface.
• Extract S-parameter model for power rails.
• Build the testbench for the DDR simulation and the SerDes simulation.
• Build the testbench for the power transient simulation.
• Review the package and PCB layout.
• Optimize the package and PCB layout by simulation.
Yêu cầu công việc
• 1-4+ years of experience in the field of signal and power integrity
• Possess a deep knowledge of signal integrity theories, and electromagnetics
• Experience in simulation tools such as Hyperlynx, Sigrity, HSPICE, HFSS, SiWave…
• Hands-on person who is comfortable running simulations and making lab measurements, and who has done validation of simulation results using TDR, Network Analyzer, Oscilloscopes and other lab equipment
• Ability to interact effectively with other engineering disciplines
• Have excellent documentation and communication skills
• Familiar with multi-gigabit serial busses, including CCIX, PCIe, XAUI, XFI, and SFI
• Familiar with memory technologies such as DDR3/DDR4/DDR5 is preferred
• Familiar with chip/package/PCB co-design methodology
• Definition and simulation of high-speed interconnects using simulation tools
• Assess timing, noise margin, crosstalk, signal loss and signal integrity of all clocks and critical data signalling and develop noise and timing budgets
• Has done package and system-level power integrity evaluation
• Backplane design experience and analog circuit knowledge are preferred
• Ability to contribute to selection of signaling and interconnect technology
• BS/MS/ Ph.D. in Electrical Engineering/Computer Engineering or related discipline is required.